The present invention relates generally to a method for fabricating a semiconductor device, and more specifically, to a method of forming a floating body transistor used in a highly-integrated semiconductor device using a silicon-on-insulator (SOI) substrate.
In a system containing a plurality of semiconductor devices, a semiconductor memory apparatus is configured to store data generated or processed therein. For example, if a request from a data processor such as a central processing unit (CPU) is received, the semiconductor memory apparatus outputs data to the data processor from unit cells therein or stores data processed by the data processor to the unit cells, according to an address transmitted with the request.
Recently, data storage capacity of the semiconductor memory apparatus has increased, but the size of the semiconductor memory apparatus has not increased proportionally. Thus, the size of each of the multiple unit cells included in the semiconductor memory apparatus has dwindled, and the sizes of various components and elements for read or write operations has been reduced. Accordingly, components and elements duplicated unnecessarily in the semiconductor memory apparatus, such as transistors or wires, are combined or merged to decrease the area occupied by each component. Particularly, the reduction of the size of unit cells included in the semiconductor memory apparatus affects improvement of integration because the unit cells occupy one of the largest areas therein.
An example of a semiconductor memory apparatus is Dynamic Random Access Memory (DRAM), which is a type of a volatile memory device configured to retain data while a power source is supplied. The unit cell comprises a transistor and a capacitor. In the case of the unit cell having a capacitor, after the data “1” is delivered to the capacitor, charges that are temporarily stored in the storage node are dissipated, i.e., the number of charges are reduced, because of both leakage currents generated at junction of the storage nodes and inherent characteristics of the capacitor which actually lost charges while time passes. As a result, a refresh operation is periodically required on the unit cells so that data of the DRAM cannot be destroyed.
To prevent the reduction of charges, numerous methods for increasing capacitance (Cs) of the capacitor included in the unit cell have been suggested so that more charges may be stored in the storage node. For example, a prior insulating film of the capacitor, for example, an oxide film, is replaced with an advanced insulating film that has a larger dielectric constant, such as a nitrified oxide film, and a high dielectric film. Also, the capacitor having a two-dimensional structure is changed to have a three-dimensional cylinder structure or a trench structure, thereby increasing the surface of both electrodes of the capacitor.
As the design rule is reduced, the plane area where a capacitor can be formed is reduced, and it is difficult to develop materials for constituting an insulating film in the capacitor. As a result, the junction resistance value of the storage node (SN) and the turn-on resistance value of the transistor in the unit cell are greater, it is difficult to perform normal read and write operations, and refresh characteristics are deteriorated.
To improve the above-described shortcomings, the unit cell includes a transistor having a floating body. That is, the unit cell of the semiconductor memory apparatus does not include a capacitor used for storing data, but stores data in a floating body of the transistor included in the unit cell. To store data in the floating body, the voltage level supplied on the word line is reduced by ½ or ⅓ of the voltage level applied to the bit line connected to one active region of the transistor, thereby generating hot carriers. When the data “1” is delivered, a large amount of hot carriers are generated in a junction region of the bit lines BL. Then, electrons are slipped out into the bit line BL and holes remain in the floating body. When the data “0” is transmitted, the hot carriers are not generated in the junction region, and no holes remain in the floating body FB. The holes kept in the floating body lower the threshold voltage of the transistor of the unit cell; consequently the amount of current flowing through the transistor increases. That is, the amount of the current flowing when the holes are stored in the floating body of the transistor is greater than that flowing when no holes are stored. As a result, it is possible to distinguish whether the data “1” or “0” is stored in the unit cell.
The semiconductor memory apparatus that includes the floating body transistor does not include a capacitor, thereby improving the integration. However, it is difficult to prevent reduction of the number of holes that the floating body of the transistor stores because of the leakage current that occurs at the source line junction or the bit line junction. Generally, the active region of the transistor, which is connected to the bit line or the source line, includes impurities of high concentration to reduce resistance resulting from junction with metal layers. However, if the active region (e.g., source or drain region) of the transistor contains impurities of high concentration, the amount of leakage current between the active region and the floating body may increase. As a result, the number of holes stored in the floating body dissipates as time goes by. Also, since the amount of the leakage current increases in proportion to temperature, data stored in the transistor of the unit cell is easily deleted (lost) under a high temperature.
FIGS. 1a to 1e are cross-sectional diagrams illustrating a method for manufacturing a floating body transistor in a general semiconductor memory apparatus.
Referring to FIG. 1a, a gate pattern 103 including a gate electrode and a hard mask for protecting the gate electrode is formed over a silicon active region 101. The semiconductor memory apparatus including the floating body transistor is fabricated with a silicon-on-insulator (SOI) wafer including a lower insulating oxide layer 102 and the silicon active region 101 formed over the lower insulating oxide layer 102. The SOI wafer includes an insulating layer that is artificially formed between the top surface (silicon active region) and a silicon substrate to remove the impact from the silicon substrate, thereby improving the process, efficiency and characteristics of a high-pure silicon layer formed over the insulating layer. Since the SOI wafer provides a zero-defective thin silicon layer isolated with an insulating material (thermal oxide film), an insulating wall or a well-forming process is not required, so that the product developing and producing time and cost are reduced. Also, there is no burden on additional equipment investment because the equipment for general silicon wafer products is also available for SOI wafer products.
Referring to FIG. 1b, an interlayer dielectric (ILD) oxide film 104 is formed over the resulting structure including the gate pattern 103.
Referring to FIG. 1c, the ILD oxide film 104 is etched to form a self-aligned contact (SAC), thereby obtaining a contact hole 105 and an ILD oxide film 104a that remains on a spot having no contact hole 105. A part of the upper portion of the silicon active region 101 exposed between gate patterns 103 is etched.
Referring to FIG. 1d, an ion-implanting process is performed on the exposed contact hole 105 to form a landing plug contact (LPC) 108.
Referring to FIG. 1e, a polysilicon film 109 of high concentration is deposited in the exposed contact hole 105. A diffusion process is performed at a high temperature after the polysilicon film 109 is filled in the exposed contact hole 105. When the diffusion process is performed at a high temperature, the landing plug contact 108 formed in the silicon active region 101 by ion-implantation diffuses to the lower insulating oxide layer 102, thereby isolating floating bodies of each transistor.
Referring to FIG. 1e, when the diffusion process is performed at a high temperature after the polysilicon film 109 of high concentration ion-impurities are diffused vertically as well as horizontally, so that a diffusion plug 110 is formed, the horizontal diffusion may reduce the volume of the body of each transistor, and a punch-through phenomenon, whereby may occur in the upper or lower portion of the floating body formed in the silicon active region 101. Particularly, the punch-through phenomenon frequently occurs in the lower portion of the floating body having a lower concentration of impurities rather than in the upper portion of the floating body where the concentration of impurities increases by channel doping when the gate pattern 103 is formed.
In the floating body transistor fabricated over the SOI wafer, it is advantageous to isolate cells in a single active region rather than to isolate unit cells through a device isolation film by the (STI) Shallow Trench Isolation process to maximize the cell packing density. The cell packing density is the number of unit cells per length, area or volume of the memory apparatus. When the cell packing density is maximized, a unit cell having an area of 4F2 or 6F2 is formed. Herein, F is the minimum distance between fine patterns, according to a design rule.
While the size of each unit cell is reduced, the volume of the floating body is maximized so that more holes may be stored in the floating body corresponding to the data. To maximize the volume of the body of the transistor, a three-dimensional transistor having a fin region or a transistor having a plane channel region is preferably used rather than a three-dimensional transistor having a recess gate. However, when the full size of the transistor is reduced, the distance between the source and drain regions of the transistor having a plane channel region is reduced, enabling a punch-through phenomenon that is difficult to prevent.
Although the punch-through phenomenon does not occur after the diffusion process is performed at a high temperature, the horizontal diffusion reduces the volume of the floating body. If the volume of the floating body is reduced, the number of holes accumulated in the floating body that are able to correspond to data is reduced. The reduction of the floating body effect means a decrease in the capacity of storing data in unit cells for a long duration and in a sensing margin of data outputted from unit cells. That is, the operating margin of unit cells in the semiconductor memory apparatus is reduced.